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DM74ALS169B Synchronous Four-Bit Up/Down Counters
April 1984 Revised April 2000
DM74ALS169B Synchronous Four-Bit Up/Down Counters
General Description
These synchronous presettable counters feature an internal carry look ahead for cascading in high speed counting applications. The DM74ALS169B is a four-bit binary up/ down counter. The carry output is decoded to prevent spikes during normal mode of counting operation. Synchronous operation is provided so that outputs change coincident with each other when so instructed by count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive going) edge of clock input waveform. These counters are fully programmable; that is, the outputs may each be preset either HIGH or LOW. The load input circuitry allows loading with carry-enable output of cascaded counters. As loading is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. The carry look-ahead circuitry permits cascading counters for n-bit synchronous applications without additional gating. Both count enable inputs (P and T) must be LOW to count. The direction of the count is determined by the level of the up/down input. When the input is HIGH, the counter counts UP; when LOW, it counts DOWN. Input T is fed forward to enable the carry outputs. The carry output thus enabled will produce a low level output pulse with a duration approximately equal to the high portion of the QA output when counting UP, and approximately equal to the low portion of the QA when counting DOWN. This low level overflow carry pulse can be used to enable successively cascaded stages. Transitions at the enable P or T inputs are allowed regardless of the level of the clock input. The control functions for these counters are fully synchronous. Changes at control inputs (enable P, enable T, load, up/down) which modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading or counting) will be dictated solely by the conditions meeting the stable setup and hold times.
Features
s Switching specifications at 50 pF s Switching specifications guaranteed over full temperature and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s Functionally and pin-for-pin compatible with Schottky and low power Schottky TTL counterpart s Improved AC performance over Schottky and low power Schottky counterparts s Synchronously programmable s Internal look ahead for fast counting s Carry output for n-bit cascading s Synchronous counting s ESD inputs
Ordering Code:
Order Number DM74ALS169BM DM74ALS169BN Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2000 Fairchild Semiconductor Corporation
DS006207
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DM74ALS169B
Connection Diagram
Mode Select Table
LOAD L H H H H EP X L L H X ET X L L X H U/D X H L X X Action on Rising Clock Edge Load (Pn Qn) Count Up (Increment) Count Down (Decrement) No Change (Hold) No Change (Hold)
State Diagram
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DM74ALS169B
Logic Diagram
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DM74ALS169B
Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package 78.1C/W 106.8C/W 7V 7V 0C to +70C -65C to +150C
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK tSU Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency Setup Time (Note 2) Data; A, B, C, D En P, En T Load U/D tH Hold Time (Note 2) Data; A, B, C, D En P, En T Load U/D tW Width of Clock Pulse 0 15 15 15 15 0 0 0 0 13 6 8 8 10 -3 -3 -4 -4 Parameter Min 4.5 2 0.8 -0.4 8 40 Nom 5 Max 5.5 Units V V V mA mA MHz ns ns ns ns ns ns ns ns ns
Note 2: The symbol () indicates that the rising edge of the clock is used as reference.
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DM74ALS169B
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25C Symbol VIK VOH VOL II IIH IIL IO ICC HIGH Level Output Voltage LOW Level Output Voltage Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Output Drive Current Supply Current Parameter Input Clamp Voltage IOH = -0.4 mA VCC = 4.5V to 5.5V VCC = 4.5V VCC = 5.5V, VIH = 7V VCC = 5.5V, VIH = 2.7V VCC = 5.5V, VIL = 0.4V VCC = 5.5V, VO = 2.25V VCC = 5.5V -30 15 IOL = 8 mA Conditions VCC = 4.5V, II = -18 mA VCC - 2 0.35 0.5 0.1 20 -0.2 -112 25 Min Typ Max -1.5 Units V V V mA A mA mA mA
Switching Characteristics
over recommended operating free air temperature range Symbol Parameter fMAX tPLH Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output tPHL tPLH tPHL Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output VCC = 4.5V to 5.5V RL = 500 CL = 50 pF Clock Ripple Carry Conditions From To Min 40 3 20 Max Units MHz ns
Clock Clock Clock
Ripple Carry Any Q Any Q
6 2 5
20 15 20
ns ns ns
En T
Ripple Carry
2
13
ns
En T
Ripple Carry
3
16
ns
U/D (Note 3)
Ripple Carry
5
19
ns
U/D (Note 3)
Ripple Carry
5
19
ns
Note 3: Propagation delay time from up/down to ripple carry must be measured with the counter at either a minimum or a maximum count. As the logic level of the up/down input is changed, the ripple carry output will follow. If the count is minimum (0), the ripple carry output transition will be in phase. If the count is maximum, the ripple carry output will be out of phase.
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DM74ALS169B
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
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DM74ALS169B Synchronous Four-Bit Up/Down Counters
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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